Field
Embodiments described herein generally relate to interconnects within a system on chip (SOC), including reducing power consumption of the SOC using interconnect serialization/deserialization.
Related Art
SOCs can include multi-processor configurations having two or more central processing units (CPUs). In operation, applications can issue a performance request to request the SOC to provide a particular voltage and/or frequency to the corresponding CPU in which the application is running. In a conventional SOC, the other CPUs of a SOC will operate at the same voltage and frequency notwithstanding one or more CPUs requesting a lower voltage and/or frequency, thereby resulting in increased power consumption.
The exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.